Custom Op - fpgadataflow.rtl

RTL Custom Op Nodes

finn.custom_op.fpgadataflow.convolutioninputgenerator_rtl

class finn.custom_op.fpgadataflow.rtl.convolutioninputgenerator_rtl.ConvolutionInputGenerator_rtl(onnx_node, **kwargs)

Bases: ConvolutionInputGenerator, RTLBackend

Class that corresponds to finn-rtllib swg module. Generates an RTL ConvolutionInputGenerator implementation based on (System-)Verilog templates, defined in finn-rtllib/swg.

bram_estimation()

Function for BRAM resource estimation, is member function of HWCustomOp class but has to be filled by every node

code_generation_ipi()

Constructs and returns the TCL for node instantiation in Vivado IPI.

execute_node(context, graph)

Execute this CustomOp instance, given the execution context and ONNX graph.

generate_hdl(model, fpgapart, clk)

Generates HDL code and wrapper for the IP, depending on required implementation style.

get_buffer_depth()

Returns total depth of the internal buffer, depending on implementation style.

get_dynamic_config(ifm_dim=None, stride=None, dilation=None)

Returns a configuration dict to re-configure FM dimension during runtime. Stride and dilation can also be changed. Certain restrictions apply (e.g. component must be synthesized for largest buffer size).

get_exp_cycles()

Function for estimation of expected cycles for set folding, is member function of HWCustomOp class but has to be filled by every node

get_nodeattr_types()

Returns a dict of permitted attributes for node, where: ret_dict[attribute_name] = (dtype, require, default_value, <allowed_values>) - dtype indicates which member of the ONNX AttributeProto will be utilized - require indicates whether this attribute is required - default_val indicates the default value that will be used if the attribute is not set - <allowed_values> (if specified) indicates that this attribute can only be set to one of the values in the set <allowed_values>. If not specified, all values permitted by dtype are allowed.

get_number_input_values()

Function to get the number of expected input values.

get_verilog_top_module_intf_names()

Return a dict of names of input and output interfaces. The keys reflect the protocols each interface implements: ‘clk’, ‘rst’, ‘m_axis’, ‘s_axis’, ‘aximm’, ‘axilite’. Values are lists of tuples (axis, aximm) or names (axilite): ‘axis’ tuples correspond to the list of node inputs in order, each tuple is (interface_name, interface_width_bits). axilite always assumed to be 32 bits and is not tuple (name only). Each block must have at most one aximm and one axilite.

lut_estimation()

Function for LUT resource estimation, is member function of HWCustomOp class but has to be filled by every node

prepare_codegen_default()

Fills code generation dict for the default implementation style by computing the incremental addressing scheme for the circular buffer.

prepare_codegen_parallel()

Fills code generation dict for the parallel implementation style by computing the loop controller configuration and partitioning the fixed buffer into shift-registers (for parallel read access) and line buffers (for efficient LUTRAM/BRAM/URAM implementation).

prepare_rtlsim()

Creates a Verilator emulation library for the RTL code generated for this node, sets the rtlsim_so attribute to its path and returns a PyVerilator wrapper around it.

select_impl_style()

Selects implementation style based on folding configuration.

uram_estimation()

Function for UltraRAM resource estimation, is member function of HWCustomOp class but has to be filled by every node

use_parallel_window_output()

finn.custom_op.fpgadataflow.fmpadding_rtl

class finn.custom_op.fpgadataflow.rtl.fmpadding_rtl.FMPadding_rtl(onnx_node, **kwargs)

Bases: FMPadding, RTLBackend

CustomOp wrapper for the finn-rtllib fmpadding_axi component Supports adjusting the padding amount and spatial feature sizes at runtime.

code_generation_ipi()

Constructs and returns the TCL for node instantiation in Vivado IPI.

execute_node(context, graph)

Execute this CustomOp instance, given the execution context and ONNX graph.

generate_hdl(model, fpgapart, clk)

get_dynamic_config(ifm_dims=None, pads=None)

Returns a configuration dict to re-configure FM dimension and padding amounts during runtime.

get_nodeattr_types()

Returns a dict of permitted attributes for node, where: ret_dict[attribute_name] = (dtype, require, default_value, <allowed_values>) - dtype indicates which member of the ONNX AttributeProto will be utilized - require indicates whether this attribute is required - default_val indicates the default value that will be used if the attribute is not set - <allowed_values> (if specified) indicates that this attribute can only be set to one of the values in the set <allowed_values>. If not specified, all values permitted by dtype are allowed.

get_template_values(ifm_dims, pads, chans, simd, idt)

get_verilog_top_module_intf_names()

Return a dict of names of input and output interfaces. The keys reflect the protocols each interface implements: ‘clk’, ‘rst’, ‘m_axis’, ‘s_axis’, ‘aximm’, ‘axilite’. Values are lists of tuples (axis, aximm) or names (axilite): ‘axis’ tuples correspond to the list of node inputs in order, each tuple is (interface_name, interface_width_bits). axilite always assumed to be 32 bits and is not tuple (name only). Each block must have at most one aximm and one axilite.

prepare_rtlsim()

Creates a Verilator emulation library for the RTL code generated for this node, sets the rtlsim_so attribute to its path and returns a PyVerilator wrapper around it.

finn.custom_op.fpgadataflow.matrixvectoractivation_rtl

class finn.custom_op.fpgadataflow.rtl.matrixvectoractivation_rtl.MVAU_rtl(onnx_node, **kwargs)

Bases: MVAU, RTLBackend

Class that corresponds to finn-rtl Matrix Vector Unit.

dsp_estimation()

Function for DSP resource estimation, is member function of HWCustomOp class but has to be filled by every node

execute_node(context, graph)

Execute this CustomOp instance, given the execution context and ONNX graph.

generate_hdl(model, fpgapart, clk)

get_nodeattr_types()

Returns a dict of permitted attributes for node, where: ret_dict[attribute_name] = (dtype, require, default_value, <allowed_values>) - dtype indicates which member of the ONNX AttributeProto will be utilized - require indicates whether this attribute is required - default_val indicates the default value that will be used if the attribute is not set - <allowed_values> (if specified) indicates that this attribute can only be set to one of the values in the set <allowed_values>. If not specified, all values permitted by dtype are allowed.

instantiate_ip(cmd)

lut_estimation()

Function for LUT resource estimation, is member function of HWCustomOp class but has to be filled by every node

prepare_codegen_default(fpgapart, clk)

prepare_rtlsim()

Creates a Verilator emulation library for the RTL code generated for this node, sets the rtlsim_so attribute to its path and returns a PyVerilator wrapper around it.

finn.custom_op.fpgadataflow.streamingdatawidthconverter_rtl

class finn.custom_op.fpgadataflow.rtl.streamingdatawidthconverter_rtl.StreamingDataWidthConverter_rtl(onnx_node, **kwargs)

Bases: StreamingDataWidthConverter, RTLBackend

Class that corresponds to finn-rtllib datawidth converter module.

check_divisible_iowidths()

code_generation_ipi()

Constructs and returns the TCL for node instantiation in Vivado IPI.

execute_node(context, graph)

Execute this CustomOp instance, given the execution context and ONNX graph.

generate_hdl(model, fpgapart, clk)

get_nodeattr_types()

Returns a dict of permitted attributes for node, where: ret_dict[attribute_name] = (dtype, require, default_value, <allowed_values>) - dtype indicates which member of the ONNX AttributeProto will be utilized - require indicates whether this attribute is required - default_val indicates the default value that will be used if the attribute is not set - <allowed_values> (if specified) indicates that this attribute can only be set to one of the values in the set <allowed_values>. If not specified, all values permitted by dtype are allowed.

get_template_values()

prepare_rtlsim()

Creates a Verilator emulation library for the RTL code generated for this node, sets the rtlsim_so attribute to its path and returns a PyVerilator wrapper around it.

finn.custom_op.fpgadataflow.streamingfifo_rtl

class finn.custom_op.fpgadataflow.rtl.streamingfifo_rtl.StreamingFIFO_rtl(onnx_node, **kwargs)

Bases: StreamingFIFO, RTLBackend

code_generation_ipi()

execute_node(context, graph)

Execute this CustomOp instance, given the execution context and ONNX graph.

generate_hdl(model, fpgapart, clk)

get_adjusted_depth()

get_nodeattr_types()

Returns a dict of permitted attributes for node, where: ret_dict[attribute_name] = (dtype, require, default_value, <allowed_values>) - dtype indicates which member of the ONNX AttributeProto will be utilized - require indicates whether this attribute is required - default_val indicates the default value that will be used if the attribute is not set - <allowed_values> (if specified) indicates that this attribute can only be set to one of the values in the set <allowed_values>. If not specified, all values permitted by dtype are allowed.

get_verilog_top_module_intf_names()

Return a dict of names of input and output interfaces. The keys reflect the protocols each interface implements: ‘clk’, ‘rst’, ‘m_axis’, ‘s_axis’, ‘aximm’, ‘axilite’. Values are lists of tuples (axis, aximm) or names (axilite): ‘axis’ tuples correspond to the list of node inputs in order, each tuple is (interface_name, interface_width_bits). axilite always assumed to be 32 bits and is not tuple (name only). Each block must have at most one aximm and one axilite.

prepare_rtlsim()

finn.custom_op.fpgadataflow.thresholding_rtl

class finn.custom_op.fpgadataflow.rtl.thresholding_rtl.Thresholding_rtl(onnx_node, **kwargs)

Bases: Thresholding, RTLBackend

Class that corresponds to finn-rtllib ‘thresholding’ function.

bram_estimation()

return the number of BRAMs required for this node

code_generation_ipi()

Constructs and returns the TCL commands for node instantiation as an RTL block.

dump_rtl_data(dest_dir, filename, data)

Dump filled-in-template RTL files for future synthesis step

execute_node(context, graph)

Execute this CustomOp instance, given the execution context and ONNX graph.

fill_in_rtl_template_data(replace_dict, template_data)

Use attribute values to finn in RTL template placeholders

generate_hdl(model, fpgapart, clk)

Prepare HDL files from templates for synthesis

get_all_meminit_filenames(abspath=False)

Return a list of all .dat memory initializer files used for this node

get_memory_estimate()

return the memory estimate for this node

get_nodeattr_types()

Returns a dict of permitted attributes for node, where: ret_dict[attribute_name] = (dtype, require, default_value, <allowed_values>) - dtype indicates which member of the ONNX AttributeProto will be utilized - require indicates whether this attribute is required - default_val indicates the default value that will be used if the attribute is not set - <allowed_values> (if specified) indicates that this attribute can only be set to one of the values in the set <allowed_values>. If not specified, all values permitted by dtype are allowed.

get_pe_mem_geometries()

return a list of (bitwidth, depth) for PE memory configurations to be used in resource estimation

for each bitwidth, the depth is calculated as the number of thresholds that can be stored in a single memory block the bitwidth is the bitwidth of the threshold values the depth is the number of thresholds that can be stored in a single memory block the number of memory blocks is calculated as the number of thresholds divided by the depth the number of memory blocks is then multiplied by the number of PEs to get the total number of memory blocks required for the entire layer

get_rtl_file_list()

Thresholding binary search RTL file list

get_rtl_file_paths()

Get full path of all RTL files

get_rtl_template_data(path)

Return RTL file contents as a template

get_verilog_top_module_intf_names()

Return a dict of names of input and output interfaces. The keys reflect the protocols each interface implements: ‘clk’, ‘rst’, ‘m_axis’, ‘s_axis’, ‘aximm’, ‘axilite’. Values are lists of tuples (axis, aximm) or names (axilite): ‘axis’ tuples correspond to the list of node inputs in order, each tuple is (interface_name, interface_width_bits). axilite always assumed to be 32 bits and is not tuple (name only). Each block must have at most one aximm and one axilite.

lut_estimation()

return the number of LUTs required for this node

make_weight_file(weights, weight_file_mode, weight_file_name)

Produce a file containing given weights (thresholds) in appropriate format for this layer. This file can be used for either synthesis or run-time reconfig of weights.

Arguments:

• weights : numpy array with weights to be put into the file

• weight_file_name : filename for the weight file to be generated

prepare_codegen_rtl_values(model)

All dictionary values produced in this function are to replace their key value(s) in the RTL template files

prepare_rtlsim()

Creates a Verilator emulation library for the RTL code generated for this node, sets the rtlsim_so attribute to its path and returns a PyVerilator wrapper around it.

uram_estimation()

return the number of URAMs required for this node

finn.custom_op.fpgadataflow.vectorvectoractivation_rtl

class finn.custom_op.fpgadataflow.rtl.vectorvectoractivation_rtl.VVAU_rtl(onnx_node, **kwargs)

Bases: VVAU, RTLBackend

Class that corresponds to finn-rtl Vector Vector Unit.

dsp_estimation()

Function for DSP resource estimation, is member function of HWCustomOp class but has to be filled by every node

execute_node(context, graph)

Execute this CustomOp instance, given the execution context and ONNX graph.

generate_hdl(model, fpgapart, clk)

get_nodeattr_types()

Returns a dict of permitted attributes for node, where: ret_dict[attribute_name] = (dtype, require, default_value, <allowed_values>) - dtype indicates which member of the ONNX AttributeProto will be utilized - require indicates whether this attribute is required - default_val indicates the default value that will be used if the attribute is not set - <allowed_values> (if specified) indicates that this attribute can only be set to one of the values in the set <allowed_values>. If not specified, all values permitted by dtype are allowed.

instantiate_ip(cmd)

lut_estimation()

Function for LUT resource estimation, is member function of HWCustomOp class but has to be filled by every node

prepare_codegen_default(fpgapart, clk)

prepare_rtlsim()

Creates a Verilator emulation library for the RTL code generated for this node, sets the rtlsim_so attribute to its path and returns a PyVerilator wrapper around it.