End-to-End Flow

The following image shows an example end-to-end flow in FINN for a PYNQ board. Please note that you can build an IP block for your neural network for every Xilinx-AMD FPGA, but we only provide automatic system integration for a limited number of boards. However, you can use Vivado to integrate an IP block generated by FINN into your own design.

The example flow in this image starts from a trained PyTorch/Brevitas network and goes all the way to a running FPGA accelerator. As you can see in the picture, FINN has a high modularity and has the property that the flow can be stopped at any point and the intermediate result can be used for further processing or other purposes. This enables a wide range of users to benefit from FINN, even if they do not use the whole flow.

The white fields show the state of the network representation in the respective step. The colored fields represent the transformations that are applied to the network to achieve a certain result. The diagram is divided into five sections, each of it includes several flow steps. The flow starts in top left corner with Brevitas export, followed by the preparation of the network for the Vitis HLS and Vivado IPI. There is also a section for testing and verification in software (in the cloud on the right) and the hardware generation and deployment on the PYNQ board.

This example flow is covered in the end2end_example Jupyter notebooks. For a more detailed overview about the different flow sections, please have a look at the corresponding pages:

• Brevitas Export
• Network Preparation
  • Tidy-up transformations
  • Streamlining Transformations
  • Convert to HW Layers
  • Dataflow Partitioning
  • Specialize Layers
  • Folding
• Hardware Build and Deployment
  • Hardware Build
    • Driver Generation
    • DMA and DWC Node Insertion
    • Partitioning for Floorplanning
    • FIFO Insertion and IP Generation
    • Vivado/Vitis Project Generation and Synthesis
  • Deployment
• Functional Verification
  • Simulation using Python
  • Simulation using C++
  • Emulation using PyVerilator